1. Field of the Invention
This invention relates in general to the design of integrated circuits (ICs) and in particular to designing IC layouts.
2. Description of the Related Art
A number of advanced technologies are applied together in modern integrated circuit (IC) designing to achieve nanometer-scale feature sizes. One of the technologies applied is planarization. Planarization is performed during the fabrication of multi-layered ICs after the creation of each successive layer. This ensures a flat wafer surface that enables accurate fabrication of subsequent layers of the IC. Existing planarization techniques such as chemical-mechanical polishing (CMP) can yield uneven results. CMP simultaneously polishes different materials with varying hardness, for example, metal, dielectric and barrier materials in the back-end-of-line interconnect stack, or nitride and oxide in front-end-of-line shallow-trench isolation Consequently, post-planarization wafer topography becomes a function of relative proportions and patterning of different materials in a region, and can result in an uneven post-CMP wafer surface. The uneven wafer topography caused by CMP is primarily due to erosion and dishing phenomena. Erosion is a deviation in the height of a wafer surface over a large area, and is typically caused by pattern density variations at length scales of hundreds or thousands of microns. Dishing is a localized deviation in, for example, an individual conductor height due to softness of copper metal that causes extra metal removal in the middle of wide wires.
Both erosion and dishing cause variations on the surface of the IC and lead to imperfect optical lithography by acting as a source of defocus, that is, deviation from nominal of the distance between lens and wafer. Defocus can cause unforeseen lithographic errors resulting in dimensional variation in the plane of the IC being manufactured. Such variations occurring in features on polysilicon layers of the IC can result in variation of polysilicon linewidths, that is, transistor channel lengths. Variation of wire widths results when such variations occur on the interconnect layers. Further, if such variations occur on contact and via layers, then coverage area, reliability, and resistance may vary significantly from nominal. These variations are not presently accounted for in the application of reticle enhancement techniques (RETs) such as optical proximity correction (OPC), sub-resolution assist feature (SRAF) insertion, or phase-shifting mask (PSM) design.
The variation in linewidth (i.e., channel length) of a transistor device translates to large variation in leakage current of the device. Leakage current is directly proportional to leakage power dissipation and has an exponential dependence on polysilicon linewidth. It is one of the most critical challenges for ultra-deep sub-micron process technologies. Across-chip linewidth variation (ACLV) is one of the most significant contributors to leakage power variability, and causes inaccurate estimation of leakage power that degrades the results of existing leakage reduction approaches. Known leakage optimization techniques are either oblivious to ACLV or model it as a random variable, resulting in pessimistic guardbanding and over-design. This in turn causes loss of performance and parametric yield in the manufactured IC.
In light of the above discussion, there exists a need for topography-aware methods for IC analysis and optimization, and for a system that can design an optimized specification of an IC. The method and system should be capable of improving the optimization of signal delay, circuit timing, leakage power, active power, and other design metrics of manufactured ICs. The method and system should also be capable of being used within the existing IC design flow, to make use of existing and known analysis tools such as timing analysis, signal integrity analysis, power analysis, reliability analysis, and so on.